`timescale 1ns/1ns

module music_test;

reg clk;
reg rst_n;
wire music_out;

initial begin
    clk = 1'b0;
    rst_n = 1'b1;
    #100 rst_n = 1'b0;
end

always #10 clk = ~clk;

music dbt(
    .clk (clk),
    .rst_n (rst_n),
    .speaker   (music_out)
);
    
endmodule